主要设计让化学机械平坦化制程 (CMP) 都能达到可预测、稳定和一致的效能。

随着像是物联网、智慧城市、行动通讯、边缘运算等驱使世界的趋势，半导体日渐增长的记忆体和速度的需求。瓶颈来自于半导体制造过程中的化学机械平坦化(CMP)从需求到良率的持续提升，使得半导体厂无法容忍元件可靠度变异。

3M利用3M™ Trizact™ 研磨垫重新定义研磨垫产品，确保半导体化学机械平坦化制程的稳定性和一致性。

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降低变异性，提高重复性 — 改善晶圆良率

3M™ Trizact™ 研磨垫的精准设计三维显微复制表面粗糙特征

显微复制技术——微观世界的一致性

3M™ Trizact™ 研磨垫使用3M核心平台中的「显微复制技术」。此技术让我们能精准地雕刻微小特征，达成极高的表面一致性。此技术最初是因投影机的光线调控特性所诞生，现已延伸至3M成千上万的产品。

Technical paper published by The Electrochemical Society (ECS), August 2016

Within-die non-uniformity (WIDNU) determined by gate height range among 3 different devices, and by the range in dielectric thickness on top of gate (i.e., TS dielectric) between 3 different devices. One center die, one middle die, and one edge die from wafers polished with POR and MR pads are submitted for cross-sectional TEM analysis, from which gate height and dielectric thickness measurements are taken.
Authors: Wei-Tsu Tseng, Kaushik Mohan, Ricky Hull, James Hagan, Connie Truong, Duy K. Lehuu, and David Muradian

A microreplicated (MR) pad with regulated long-range order surface pore-asperity patterns is used for the buff polish step in a 3-platen W-CMP process for 14 nm replacement metal gate (RMG) and trench salicide (TS) planarization. This new pad requires no diamond tip conditioner and can last up to 2000 wafer passes with highly repeatable removal rates, while maintaining low and consistent defects and within-wafer uniformity. The MR pad also provides unique benefits of mitigating within-die non-uniformity as demonstrated by gate electrical conductance tests and confirmed by physical thickness measurement through cross-sectional TEM.

In addition, topography-driven defects are reduced significantly. The mechanisms responsible for the unique performance of MR pads will be elucidated and the significance of this new CMP pad technology will be discussed.

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